There are four possible reasons for this problem:
- The trigger condition is never met;
- The trigger clock (clock mapped to the ILA Core) is stopped;
- A known issue exists with the Storage Qualification feature;
- BUFG is not being used on JTAG CLK (for the ICON).
The trigger condition is never met
Check the message at the bottom of the ChipScope Analyzer window. If it is similar to "Waiting for trigger, Sample buffer has 0 samples(0%)," proceed as follows:
1. Go to "Trigger Setup" and "Trigger Immediate." If ChipScope Analyzer starts the acquisition and shows the samples (the waveform appears), your design is fine; the clock is running, but your trigger condition never occurs.
2. In the "Trigger Setup windows, ensure that you have set the condition correctly if you are sure that this event (the trigger condition) happens in your design.
The trigger clock is stopped
If the message at the bottom of the window is similar to "Waiting for Core to be armed, slow or stopped clock," the trigger condition is not the problem -- the ILA Core does not have a valid clock and is not able to start the acquisition. To fix this, ensure that you have mapped a valid clock (in ChipScope Inserter or ChipScope Generator). If you are not sure if the clock mapped to the ILA Core is running, try to connect your system clock instead (or a clock that you are sure is running).
Known issue with Storage Qualification feature
There is a known issue with ChipScope Pro 7.1 sp1/sp2 on the following architectures:
In the Storage Qualification settings (in both ChipScope Pro Generator and ChipScope Pro Inserter), "Enable Storage Qualification" is selected by default. This feature is not supported on the above architectures and must be disabled. This option will be greyed out in the next service pack (as it was in ChipScope Pro 6.3).
BUFG is not used on ICON's JTAG clock
If the JTAG clock does not use a BUFG, the "Waiting for upload" message can appear.
In some instances, slowing down the cable speed might provide a suitable work-around.