The Power-On Reset voltage for each supply is as follows:
VCCINT 0.4 1.0V
VCCAUX 0.8 2.0V
VCCO (Bank 4) 0.4 1.0V
On power up, the Spartan-3/-3E FPGAs internal Power-On Reset (POR) circuit is triggered when the following conditions are met:
VCCINT > 1.0V
VCCAUX > 2.0V
VCCO (Bank 4) >0 1.0V
For more information on Spartan-3/-3E power-on requirements, see (Xilinx Answer 17208).
During device operation (after a successful power-on), the internal Power-On Reset circuit is triggered when one of the following conditions is met:
VCCINT < 0.4 V
VCCAUX < 0.8 V
NOTE: After initial power-up, the internal POR circuitry no longer monitors VCCO in bank 4. Therefore, if VCCO drops below its minimum POR threshold, a POR will not occur. The VCCINT and VCCAUX voltages mentioned above reflect the minimum POR threshold for the respective supplies. Please note that if the voltage drops below Vdrint(1.0V) or Vdraux(2.0V), the RAM content can no longer be guaranteed as these are power voltage levels necessary for preserving RAM content. Since the minimum POR thresholds are set lower than Vdrint and Vdraux, it is not guaranteed that POR will occur if the voltage drops below Vdrint or Vdraux. Therefore, it is possible that RAM content might not be retained in this situation and the design might operate with an erroneous RAM configuration. In this case, it is recommended to drop either VCCINT or VCCAUX below its minimum POR threshold to initiate a POR.
For more information on what happens when VCCO, VCCINT, or VCCAUX is lost during device operation, see (Xilinx Answer 19965).
For questions related to the Spartan-6 POR, see (Xilinx Answer 40911).
For additional details on power on specifications, see the Spartan-3 DC and Switching Characteristics Data Sheet (DS099):
For additional details on power on specifications, see the Spartan-3E DC and Switching Characteristics Data Sheet (DS312):
Other relevant references include:
Spartan-3 Generation FPGA User Guide (UG331):
Spartan-3 Generation Configuration User Guide (UG332):