UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20724

Spartan-3/-3E/-3A, DCM - What is the reset requirement for the DCM?

描述

What is the reset requirement for the Spartan-3/-3E/-3A DCM?

解决方案

The reset input must be asserted at least 3 valid CLKIN cycles.

For more information on Spartan-3/-3E/-3A DCM functionality, see the Spartan-3 Generation FPGA User Guide at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
Choose FPGA Device Families -> Spartan-3/3L -> "Spartan-3 Generation FPGA User Guide" -- (UG331)

For more information on Spartan-3/-3E/-3A DCM specifications, see the DC and Switching Characteristic section of the Data Sheets located at:

Spartan-3:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
Choose FPGA Device Families -> Spartan-3/3L -> "Spartan-3 Complete Data Sheet (All four modules)" -- (DS099)

Spartan-3E:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
Choose FPGA Device Families -> Spartan-3E -> "Spartan-3E Complete Data Sheet (All four modules) -- (DS312)

Spartan-3A:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
Choose FPGA Device Families -> Spartan-3A -> "Spartan-3A FPGA Family Data Sheet"--(DS529)

AR# 20724
日期 10/16/2013
状态 Active
Type 综合文章
的页面