UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20776

6.3 System Generator for DSP - Why do I receive "Continuous sample times not allowed for downsample blocks" when doing a Hardware in the Loop (HITL) Co-Simulation of my model?

描述

General Description:

Why do I receive "Continuous sample times not allowed for downsample blocks" when doing a Hardware in the Loop (HITL) Co-Simulation of my model?

解决方案

This can be caused by very small sample times, or by not having a sample time set for all the inputs to the System Generator for DSP Model.

You can try the following to see if these methods resolve the problem:

1. Set the input blocks to the System Generator for DSP model with a sample time, instead of 0, which tells Simulink use continuous sample time.

2. Add Gateways to the inputs of your Hardware in the Loop block.

3. You can also try adding Zero Order hold blocks from the Simulink Blocksets, after the Gateway outs in the subsystem where the Hardware in the Loop Co-Simulation block is located.

AR# 20776
日期 12/15/2012
状态 Active
Type 综合文章
的页面