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AR# 21594

Spartan-3, DCM - CLKFX outputs undesired periods when CLKIN inputs have excessive jitter


DCM CLKFX sometimes outputs a clock pulse that does not have the correct period. What could be causing these unwanted periods?


The CLKFX outputs can potentially have abrupt period shifts if the CLKIN inputs have excessive jitter. These shifts might occur at every clock "concurrence." Clock "concurrences" are the times when the rising edges of the input clock and the output clock are (or should be) in phase. It occurs every D cycles of CLKIN, and every M cycles of CLKFX.

The following diagram provides an example of when CLKFX is used with M=7 and D=5:

Hard Phase Alignment Image 1
Hard Phase Alignment Image 1

The DCM DFS circuit (which creates the CLKFX output) has logic to determine every clock concurrence. At each concurrence, the CLKIN rising edge is automatically transferred onto the CLKFX rising edge. This is how CLKFX keeps the phase relationship with CLKIN. Thus, if the CLKIN input has excessive jitter, CLKFX output will match the phase of that jittery clock at every concurrence. This could result in a sudden increase/decrease in the output pulse, as shown in the example below:

Hard Phase Alignment Image 2
Hard Phase Alignment Image 2

The abrupt shifts at the clock concurrence can be avoided by ensuring thejitter at the DCM input pin does not exceed the jitter requirements of CLKIN provided in the Device Data Sheet. The DFS is robust and can often continue to output CLKFX even when the jitter is higher than specification, although not guaranteed. During this high input jitter operation,it has been observed that when a large shift at concurrence happens, typically larger than CLKFX period shift, the CLKFX output will stop toggling. When CLKFX stops toggling, the STATUS[2] bit will assert prompting that the DFS can no longer compensate for the CLKIN and CLKFX period jitter difference.
The DLL portion of the DCM can also follow the input clock period drift over time. However, when the M and D values are both large, the frequency compensation is reduced and cannot catch up with frequency drift. Because of this, higher M and D values make the DCM more susceptible to abrupt shifts, and in the extreme case willresult inthe CLKFX stop condition. It is important to note that the CLKFX stop conditions have only been seen in instances when the input clock jitter to the DCM input pin exceeded the jitter requirement of CLKIN.

It is always good design practice to monitor the STATUS output signals out of the DCM. If STATUS[2] goes high, indicating the CLKFX output has stopped, a RESET of the DCM is required. If the LOCK output goes low, indicating the DCM has lost its frequency or phase alignment and calibration to the input clock, then a RESET of the DCM is required. In these cases, a RESET will allow the DCM to obtain LOCK on the input clock and resume normal operation.

Please refer to (Xilinx Answer 19827) for more information on DCM jitter.

AR# 21594
日期 12/15/2012
状态 Active
Type 综合文章
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E