When using COREGen, I receive the following error:
"ERROR:HDLCompilers:175 - Source file <> does not exist"
This error is generated if the Verilog wrapper file for the core is not in the same directory as the main project directory.
To obtain the module declaration for the core, XST needs to parse the information for the wrapper file. If it cannot find the wrapper file, it will result in an error.
The best way to fix this problem is to copy the wrapper file to the project directory.
Alternatively, place the directory where the wrapper file resides in the Verilog Include Directories properties. For information on how to set this option, see the latest XST User Guide at: