This is a known problem that has been found on various designs from ISE 7.1i and IDS 10.1.03.
The problem occurs because MAP is attempting to optimize the design by pulling registers out of or into the DSP48 slices. However, in some cases, it is adding registers to the DSP48 slice inputs. This added latency breaks the synchronization and causes problems in hardware and post-PAR simulation, which causes a mismatch with behavioral simulation.
The first recommendation by which to work around this problem is to try the latest release of the Xilinx ISE Implementation tools, as this issue might be fixed in the latest release.
Second, if it is not resolved in the latest release of the ISE Implementation tools, you can work around this problem by setting the following environment variable on your system:
XIL_MAP_NO_DSP_AUTOREG = 1
For information on setting environment variables, see (Xilinx Answer 11630).
If the environment variable does fix your design, please open a case with Xilinx Technical Support so that this issue can be addressed: