Why do the Simulink Sample Time Colors change when simulating my System Generator for DSP design?
If you perform a model update (Ctrl-D), the sample time colors will display correctly.
However, when a simulation is run, the Xilinx blocks are perceived to have a different sample time.
This is the expected behavior and does not affect the generated hardware sample rates.
Currently, there is no way to work around this display problem.
Xilinx recommends that you turn off the sample time colors in Simulink and use the System Generator for DSP Sample Rates, Block Icon Display option.
This option is available from the System Generator Token.