This Release Note is for the SPI-4.2 (POS-PHY L4) v8.1 Core released in 8.2i IP Update 1; it contains the following information:
- New Features
- Bug Fixes
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 23479)
New Features in v8.1
Supports ISE 8.2i
Supports Virtex-5 (up to 800 Mbp in -1 speed grade)
Added new signal pin SrcStatFrameErr to flag incorrect frame words received on TStat
Supports insertion of IDELAY module in RDClk path
Dynamic Phase Alignment (DPA) clock adjustment (Virtex-4 Only)
Full rate clock (RDClk0_GP) generation using DCM
New DPA RAM output to assist board-level debugging
Inversion of SPI-4.2 Source Outputs to assist board-level debugging
Bug Fixes in v8.1
CR 218645 : SnkBusErr should not be asserted during clk-data alignment
CR 221524 : Error:sim:158 - Tcl error detected while configuring symbol pin. Corrected by disabling symbol ASY file generation.
CR 226187 : Internal clock generation with PMCD is valid only for DPA with Continuous Alignment option
CR 206779 : "Fatal: (vsim-3421) Value 512 is out of range 0 to 511" error seen when demonstration testbench fails to load in simulation when length of calendar sequence exceeds 510
CR 215240 : NGDBuild fails when example DIFF_TERM constraints are applied to inputs
- Version 8.1 of the SPI-4.2 Core supports Virtex-4 and Virtex-5 family. For Virtex-II and Virtex-II Pro designs, use the latest version of the v6.x series of the SPI-4.2 Core.
- The Version 8.1 Core is compatible with ISE 8.2i Service Pack 1.
- If you are using multiple SPI-4.2 Cores in a single device, you must generate the core with a unique component name for each instance. See the "Multiple Core Instantiation" section under the "Special Design Consideration" chapter of the SPI-4.2 User Guide.
(Xilinx Answer 23667) Migrating SPI4.2 design from v7.4 to v8.1
(Xilinx Answer 23668) Migrating SPI4.2 design from v6.3 to v8.1
(Xilinx Answer 21386) When do I use Global Clocking vs Regional Clocking?
(Xilinx Answer 21069) When using Dynamic Phase Alignment or the SPI Core, RDClk must be running at least 220 MHz minimum.
(Xilinx Answer 20430) What is the power consumption of SPI-4.2 Core?
(Xilinx Answer 15500) How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM?
(Xilinx Answer 20017) Which I/O Standards are supported for the SPI-4.2 Core?
(Xilinx Answer 21959) When I simulate an SPI-4.2 design with DCM standby logic, only timing simulation with SDF is supported.
(Xilinx Answer 22392) When using a Source Core with Slave Clocking, use clocks from another Master Source core, not the general-purpose clock from the Sink core.
Known Issues in v8.1
GUI and Core Generation Issues
(Xilinx Answer 23771) When generating the core, GUI allows illegal clocking options.
Constraints and Implementation Issues
(Xilinx Answer 23681) When targeting Virtex-5, SPI-4.2 design with "Insert IDELAY on RDCLK" feature selected, MAP gives error.
(Xilinx Answer 23683) When targeting Virtex-4, SPI-4.2 design with "Insert IDELAY on RDCLK" feature selected, PAR gives error.
(Xilinx Answer 20000) When implementing an SPI-4.2 design through NGDBuild, several "WARNING" and "INFO" messages appear.
(Xilinx Answer 21439) When implementing an SPI-4.2 design through MAP, several "WARNING" and "INFO" messages appear.
(Xilinx Answer 21320) When implementing an SPI-4.2 design through PAR, several "WARNING" and "INFO" messages appear.
(Xilinx Answer 21363) PAR has problems placing components or completely routing the SPI4.2 design in my design.
(Xilinx Answer 20280) Placement failures occur in PAR when the SPI-4.2 FIFO Status Signals' I/O Standard is set to LVTTL I/O.
(Xilinx Answer 20040) Timing Analyzer (TRCE) reports "0 items analyzed."
(Xilinx Answer 19999) "ERROR:BitGen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported."
(Xilinx Answer 20319) When running implementation, undefined I/O (single-ended) defaults to LVCMOS causes WARNINGS in NGDBuild.
(Xilinx Answer 20017) The SPI-4.2 Core signals default to LVDS without the internal device termination. If internal termination is needed, it must be defined in the UCF. For a complete list of supported I/O, see (Xilinx Answer 20017).
General Simulation Issues
(Xilinx Answer 23680) Timing simulation not supported for Virtex-5 designs.
(Xilinx Answer 21409) When using Dynamic Phase Alignment, the PhaseAlignComplete signal is not asserted and SnkOof is never de-asserted.
(Xilinx Answer 21319) When running timing simulation on an SPI4.2 Design Example, several "TDat Error: Data Mismatch" messages are reported.
(Xilinx Answer 21321) When running timing simulation on an SPI4.2 design with a Sink core set to Dynamic Alignment mode, several "Error: */X_ISERDES SETUP Low - - VIOLATION ON D WITH RESPECT TO CLK" messages are reported.
(Xilinx Answer 21322) When running timing simulation on a SPI4.2 design, several SETUP, HOLD, and RECOVERY violations occur.
(Xilinx Answer 21362) When running Verilog timing simulation, TDat output is always "0000" and no training pattern is sent after reset.
(Xilinx Answer 20030) When simulating an SPI-4.2 design, multiple warning messages are expected at the beginning of the simulation.
(Xilinx Answer 15578) When simulating an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur.
(Xilinx Answer 21316) When running timing simulation using the design example, DIP2 mismatch errors occur in the simulator.
(Xilinx Answer 21959) When simulating an SPI-4.2 design with DCM standby logic, only timing simulation with SDF is supported.
(Xilinx Answer 20796) When targeting a Virtex-4 design with the SPI4.2 Core, a silicon issue exists.
(Xilinx Answer 20022) When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations.
- When I open the SPI4.2 GUI in COREGen using the Hardware timeout evaluation license, it displays a pop-up message. The message indicates that the Hardware timeout lasts for 6-8 hours. However, the core will run only 2 hours.
SPI- 4.2 (PL4) v7.4 KNOWN ISSUES
- The SPI-4.2 v7.4 Core is now obsolete. Please upgrade to the latest version of the core.
For information on existing SPI-4.2 v7.4 issues, see (Xilinx Answer 22300).
SPI- 4.2 (PL4) v7.3 KNOWN ISSUES
- The SPI-4.2 v7.3 Core is now obsolete. Please upgrade to the latest version of the core.
For information on existing SPI-4.2 v7.3 issues, see (Xilinx Answer 21918).
SPI- 4.2 (PL4) v7.2 KNOWN ISSUES
- The SPI-4.2 v7.2 Core is now obsolete. Please upgrade to the latest version of the core.
For information on existing SPI-4.2 v7.2 issues, see (Xilinx Answer 21032).
SPI- 4.2 (PL4) v7.1 KNOWN ISSUES
- The SPI-4.2 v7.1 Core is now obsolete. Please upgrade to the latest version of the core.
For information on existing SPI-4.2 v7.1 issues, see (Xilinx Answer 20274).