This Answer Record contains the Release Notes and Known Issues for System Generator for DSP 9.2.01.1028.
For System Generator for DSP Release Notes from other release versions, see (Xilinx Answer 29595).
Known Issues in System Generator for DSP 9.2.01
System Generator for DSP 9.2.01 is a minor update. Please read the documentation, as it answers questions you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The System Generator User Guide is accessible in PDF format at:
Support Software Issues
- What software is required to install System Generator for DSP? See (Xilinx Answer 17966).
- How do I enable Virtex-5 SXT support or other devices installed to ISE after System Generator was installed? See (Xilinx Answer 24158).
Xilinx Block Set Issues
-The System Generator EDK export flow supports only a 32-bit PLB bus. See (Xilinx Answer 29633).
- I receive the message "Index exceeds matrix dimensions" when I click the EDK import button from System Generator. See (Xilinx Answer 29181).
- For Spartan-3A DSP designs, XST is incorrectly used for synthesis when Synplify Pro is specified. See (Xilinx Answer 29142).
- Why does the design fail to generate when using a FIFO block, From FIFO block, or To FIFO block in the design, and the target path is more than 160 characters? See (Xilinx Answer 23614).
- Why do the outputs of a FROM and TO register appear to be incorrect when I use the Free Running Clock with Hardware in the Loop (HITL) Co-Simulation? See (Xilinx Answer 23206).
- Why do errors occur when I try to generate an EDK PCORE from System Generator with a single shared memory block larger than 256 in depth? See (Xilinx Answer 30664).
- Generation fails when the Simulation Stop Function is defined for a model. See (Xilinx Answer 18623).
- User Hardware Co-Sim files disappear when installing System Generator for DSP update. See (Xilinx Answer 18646).
- Why do I see an instantiated register called "xlpersistentdff" in a System Generator for DSP design? See (Xilinx Answer 24257).
- JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. See (Xilinx Answer 19599).
- Why do I receive "Error evaluating 'OpenFcn' callback of Xilinx Block. Error using ==> xlOpenGui" Cannot parse XLM file" when I try to open a SysGen block on a network installation, or after installing a new version. See (Xilinx Answer 23223).
- Why do I receive "Error 0001: caught standard exception" error when using IBM Clear Case? See (Xilinx Answer 24263).
- Why do post-PAR simulation mismatches occur when running a design at faster than 200 MHz? See (Xilinx Answer 24268).
- I cannot generate an NGC, Bitstream, Timing Analysis, or Hardware in the Loop target when using Synplify as my synthesis tool. Why? See (Xilinx Answer 24273).
- Why do I receive the error message "All Xilinx Blocks must be contained in a level of hierarchy with a System Generator Token" when I use the multiple subsystem generator flow or have my token in a subsystem? See (Xilinx Answer 24845).
- When my model is opened with MATLAB 2006b from Windows Explorer by double-clicking the model, an internal error occurs when I try to simulate. See (Xilinx Answer 24867).
- I am having some problems running network-based Ethernet Co-Simulation with the ML506 board. See (Xilinx Answer 24868).
- Why are there simulation mismatches at the beginning of the HDL simulation generated from System Generator for DSP when Synplify is used for synthesis? See (Xilinx Answer 29170).
- When I run hardware co-simulation with my RoHS Compliant Virtex-4 XtremeDSP Kit, error message occurs: "Unable to locate XtremeDSP Kit board using the PCI interface". See (Xilinx Answer 30294).