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AR# 3143

14.x Timing Analysis - Analysis of paths to and through RAM

Description

What paths will Timing Analyzer control in regards to different types of RAM?

解决方案

For Asynchronous RAM:

- Paths that end at RAM are traced, including the WE, D, and Address pins. Trace should determine the setup time.
- Paths that start at RAM are traced. Trace determines the worst-case time from a change on D or WE to data valid (and on to the destination).
- Paths that propagate through RAM are traced if they arrive at the address pins, but not if they arrive at the D or WE pins. A change on an address pin propagates just as it would for ordinary LUTs. However, propagation of changes on D or WE are assumed to be of interest only when the RAM is being read during a write operation.
If you want PAR to control the delay on paths through the D or WE inputs, you must split the delay requirement into two segments: one ending at the RAM input pin, and the other beginning at the RAM output.

For Single-Port Synchronous RAM:

- Paths that end at RAM are traced, including the WE, D, and Address pins. PAR determines the setup time with respect to the WCLK pin.
- Paths that start at RAM are traced. PAR determines the worst-case time after WCLK transition to data valid.
- Paths that propagate through RAM are traced if they arrive at the address pins, but not if they arrive at the D or WE pins. A change on an address pin propagates just as it would for ordinary LUTs. However, propagation of changes on D or WE are assumed to be of interest only when the RAM is being read during a write operation.

If you want PAR to control the delay on paths through the D or WE inputs, you must split the delay requirement into two segments: one ending at the RAM input pin, and the other beginning at the RAM output.

For Dual-Port Synchronous RAM:

- Paths that end at RAM are traced, except for the paths that end at the DPRA0 to DPRA3 pins. Read address inputs cannot impact paths that end at a RAM (write function).
- Paths that start at RAM are traced. PAR determines the worst-case time after WCLK transition to data valid.
- Paths that propagate through RAM are traced if they arrive at the address pins (A* to SPO paths and DPRA* to DPO paths), but not if they arrive at the D or WE pins. A change on an address pin propagates just as it would for ordinary LUTs. However, propagation of changes on D or WE are assumed to be of interest only when the RAM is being read during a write operation.

If you want PAR to control the delay on paths through the D or WE inputs, you must split the delay requirement into two segments: one ending at the RAM input pin, and the other beginning at the RAM output.

AR# 3143
创建日期 08/21/2007
Last Updated 12/15/2012
状态 Active
Type 综合文章
器件
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