I have a design that uses the SPI, ZBT RAM, and STARTUP_VIRTEX5. At some point during the program's execution, data from the RAM becomes corrupted.
Why does this occur?
The clock enable control lines between the Strata flash and the SPI flash are shared. The data lines between the Strata flash and the ZBT RAM are shared. When the SPI flash is enabled, the Strata flash is also enabled causing contention on the upper 16 bits of the ZBT RAM data lines.
The SPI flash CE signal is separated from the Strata flash CE signal by a 1K Ohm resistor. The work-around is to drive a "1" on pin AE14 (Strata flash CE pin) in the FPGA to cause the Strata flash to be disabled.