The example simulation testbench writes to the Endpoint's Device Control Register. However, the register number written is incorrect. It writes address 60h instead of 68h.
解决方案
For a description of the register space in the Endpoint Block Plus Core, see The Endpoint Block Plus User Guide (UG341); Chapter 2, PCI Configuration Space.
The Device Control Register is at address 68h.
To fix this:
Verilog File pci_exp_usrapp_tx.v
Find the task TSK_BAR_PROGRAM and change the last configuration write to be as follows:
09/16/2009- Updated for ISE 11.3 and core version v1.12. 06/24/2009 - Updated for ISE 11.2 and core version v1.11 04/13/2009- Updated for ISE 11.1 and core version v1.10. 10/28/2008 - Initial Release.