I have my EDK design instantiated in an ISE project. I have already synthesized and implemented my EDK project in ISE. I now change my instantiation template from VHDL to Verilog (or from Verilog to VHDL). My EDK project is now re-synthesizing and re-implementing.
Why did the change in the template language cause my project to rebuild?
When an EDK project is instantiated in an ISE project, the EDK project receives its preferred HDL setting from ISE's language template setting. When the language template setting is changed, an EDK source file (the platgen.opt file) is changed, thus necessitating a rebuild of the EDK project.