This Release Note and Known Issues Answer Record is for the LogiCORE IP Initiator/Target for PCI v3.167 released in ISE Design Suite 11.1, and it contains the following information:
For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf.
General Information
The LogiCORE IP PCI v3.167 supports only Virtex-4, Spartan-3, and older architectures. For Virtex-5 devices, use the v4.8 PCI Core. For more information on this core, refer to (Xilinx Answer 31568).
For general information regarding timing closure in Virtex-4 devices, see (Xilinx Answer 22921).
New Features
Resolved Issues
Known Issues
(Xilinx Answer 47089) -Initiator/Target for PCI v3.167 - Fails with Java error in ISE software versions13.4, 13.3, and 13.2
(Xilinx Answer 32498) - LogiCORE IP Initiator/Target v3.167 for PCI - The v3.167 Core does not show up under default CORE Generator view
(Xilinx Answer 32499) - LogiCORE IP Initiator/Target v4.8 and v3.167 - Simulation Error:$hold( posedge CLK:18310587 ps, posedge I &&& (in_clk_enable1 == 1):18310595 ps, 50 ps );
Revision History
04/05/2012 - Added Answer Record 47089
06/17/2009 - Added MTI note on vsim command
09/19/2008 - Initial Release
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
47089 | Initiator/Target for PCI v3.167 - Fails with Java error in ISE tool versions 13.2 to 14.2 | N/A | N/A |
AR# 32324 | |
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日期 | 12/15/2012 |
状态 | Active |
Type | 综合文章 |
IP |