Keywords : XC9500, XC9500XL, XPLA3, CoolRunner, CoolRunner-II
Is Abel supported for CPLD design entry in the 11.1 ISE release?
No. ABEL is not supported for CPLD design entry in 11.1 ISE. If you open a project in 11.1 that has an ABEL source, you will receive the following warning message in the Warning tab:
"WARNING: ABEL sources (jc2_top.abl) are no longer supported in the current release of ISE, the converted HDL sources will be added to the project instead.
WARNING: the generated hdl for jc2_top.abl was not found, your migrated design may be incomplete."
To work around this issue, you can continue to use 10.1 ISE, or you can use 10.1 (or a previous version of ISE) to convert your ABEL file into VHDL or Verilog. In 10.1 ISE the ABEL source is compiled and converted into either VHDL or Verilog before XST synthesizes it. The VHDL file has the extension ".vhf", and the Verilog file has the extension ".vf". You can rename the files as ".vhd" or ".v" and use them in 11.1.