Running timing simulation on the PING design or user designs might result in the following warnings:
# ** Error:/xilinx//verilog/src/simprims/X_FF.v(101): $hold( posedge CLK:18310587 ps, posedge I &&& (in_clk_enable1 == 1):18310595 ps, 50 ps );
# Time: 18310595 ps Iteration: 1 Instance: /ping_tb/UUT/\PCI_CORE/XPCI_ADQ30
# ** Error: /xilinx/verilog/src/simprims/X_FF.v(101): $setup( posedge I &&& (in_clk_enable1 == 1):18310599 ps, posedge CLK:18310640 ps, 79 ps );
# Time: 18310640 ps Iteration: 2 Instance: /ping_tb/UUT/\PCI_CORE/XPCI_ADQ17
These errors are expected if they occur when the core is not actively engaged in a transfer. Typically, this happens when the core stops driving the bus and transitions to driving HI-Z in the simulation. Hi-Z is seen by the inputs of the core causing Xs to propagate through the model which causes this error to be reported by the simulator.
Users should evaluate each error and determine if it is a legitimate timing concern or due to this reason. The core is actively engaged in a data transfer when both IRDY# and TRDY# are asserted.
04/13/2009 - Initial Release