AR# 32707

12.1 Timing Analyzer - IODELAY Min, Maximum Delay information

描述


The Virtex-5 FPGA data sheet mentions to look at the Timing Analyzer report for the calculation part of the delay in relation to IODELAY block. However, the same delay information in the speed print indicates that the MIN delay is more than the MAX delay.
Why the discrepancy?

解决方案

True, the speed print actually mentions that the MIN delay is larger than the MAX delay.MIN delay adjusts hold time, whereas, MAX delay adjusts setup time.The speed file manipulates the delay values to ensure that the implementation tools match what is characterized in the hardware.
AR# 32707
日期 05/19/2012
状态 Active
Type 已知问题
器件 More Less
Tools More Less