AR# 32766


SPI-4.2 v9.2 - Release Notes and Known Issues for ISE 11.2


This Release Notes and Known Issues Answer Record is for the SPI-4.2 (POS-PHY L4) v9.2 Core, released in ISE 11.2, and contains the following information:

- New Features

- Bug Fixes

- General Information

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:


New Features in v9.2

- ISE 11.2 software support

- Virtex-6 support

Bug Fixes in v9.2

- None

General Information

-Virtex-6 CXT devices are supported with the following performance:

-1 speed grade: up to 700 Mb/s ( static and dynamic configurations)

-2 speed grade: up to 700 Mb/s ( static configuration )

-2 speed grade: up to 800 Mb/s ( dynamic configuration )

(Xilinx Answer 32917) Virtex-6 change to HIGH_PERFORMANCE_MODE attribute for IODELAYE1 elements in UCF

- If you are using multiple SPI-4.2 Cores in a single device, you must generate the core with a unique component name for each instance. See the Multiple Core Instantiation section under the Special Design Considerations chapter of the SPI-4.2 User Guide.

(Xilinx Answer 15500) How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM?

(Xilinx Answer 20017) Which I/O Standards are supported for the SPI-4.2 Core?

(Xilinx Answer 32942) Changing static configuration signals in-circuit

Known Issues in v9.2

Constraints and Implementation Issues

- For Virtex-6 devices:

- Virtex-6 solutions are pending hardware validation

- Support ModelSim MTI and Synopsys VCS simulation only

- Sink DPA Clock Adjustment option for Global Clocking Mode is not supported

(Xilinx Answer 32628) "ERROR:PhysDesignRules:1613 - IDELAYCTRL not found for clock region..." message during Map for Sink core

(Xilinx Answer 32632) "ERROR:Place:909 - Regional Clock Net "core_pl4_src_top0/tsclk_gp" cannot possibly be routed..." message during Map for Source core

(Xilinx Answer 20000) When implementing an SPI-4.2 design through NGDBuild, several "WARNING" and "INFO" messages appear

(Xilinx Answer 21439) When implementing an SPI-4.2 design through MAP, several "WARNING" and "INFO" messages appear

(Xilinx Answer 21320) When implementing an SPI-4.2 design through PAR, several "WARNING" and "INFO" messages appear

(Xilinx Answer 21363) PAR has problems placing components or completely routing the SPI4.2 design in my design

(Xilinx Answer 20280) Placement failures occur in PAR when the SPI-4.2 FIFO Status Signals' I/O Standard is set to LVTTL I/O

(Xilinx Answer 20040) Timing Analyzer (TRCE) reports "0 items analyzed"

(Xilinx Answer 20319) When running implementation, undefined I/O (single-ended) defaults to LVCMOS causes WARNINGS in NGDBuild

General Simulation Issues

(Xilinx Answer 32916) Virtex-6 Verilog timing simulation does not work with SDFMAX

(Xilinx Answer 32617) NCSim produces error for DCM DLL_FREQUENCY_MODE

(Xilinx Answer 32618) NCSIM timing simulation does not work with SDF file

(Xilinx Answer 32619) Static alignment core might not go into frame in VCS timing simulation

(Xilinx Answer 32627) Sink core might not align or go in frame in VCS simulation

(Xilinx Answer 24027) Compiling XilinxCoreLib gives error: "Error-[URMI] Instances with unresolved modules remain in the design"

(Xilinx Answer 24026) When I run simulation on SPI-4.2 design, Locked_RDClk (from RDClk DCM) might get de-asserted after PhaseAlignRequest

(Xilinx Answer 21319) When I run timing simulation on an SPI-4.2 design example, several "TDat Error: Data Mismatch" messages are reported

(Xilinx Answer 21321) Timing simulation error: # ** Error: */X_ISERDES SETUP Low VIOLATION ON D WITH RESPECT TO CLK;

(Xilinx Answer 21322) When I run timing simulation on a SPI4.2 design, several SETUP, HOLD, and RECOVERY violations occur

(Xilinx Answer 20030) When I simulate an SPI-4.2 design, multiple warning messages are expected at the beginning of the simulation

(Xilinx Answer 15578) When I simulate an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur

Revision History

06/24/2009 - Initial Release

AR# 32766
日期 12/15/2012
状态 Active
Type 综合文章
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