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MIG Virtex-6 FPGA DDR2/DDR3 - False memory model violations might occur in simulation
The OCB functionality in the MIG Virtex-6 FPGA DDR2/DDR3 SDRAM design causes small clock phase adjustments to be made dynamically.
The phase adjustments can be a few taps (10's of ps in scale).
If you are running at a boundary frequency case, (for example a clock period of 15.000 ns) one of the phase adjustments can adjust the clock to occur 14.956 ns away from the last clock edge.
A memory model checker could cause an error because it expects tWR to be 15 ns and 14.956 violates this specification.
Simulations could generate false memory model errors in these situations.
Errors that occur due to dynamically adjusted clock phases in these boundary frequency cases can be ignored, as this is not an issue in a real system (hardware).
To prevent these errors, increase the clock period by one step of the minimum resolution.
- Virtex-6 CXT
- Virtex-6 HXT
- Virtex-6 LX
- Virtex-6 LXT
- Virtex-6 SXT