描述

When using Synplify Pro C-2009.02 for synthesis, MIG Virtex-5 Verilog designs fail in MAP. This is because Synplify Pro C-2009 does not properly identify the IODELAY_GROUP attribute. An error is not generated during synthesis, however, an incorrect value exists in the generated EDIF, which causes the design to fail during MAP with the following error:

"ERROR:MapLib:1114 - IDELAYCTRL symbol "u_ddr_idelay_ctrl/u_idelayctrl" (output signal=idelay_ctrl_rdy) has IODELAY_GROUP property "IODELAY_MI". But the design does not contain DELAY element with the same IODELAY_GROUP name."

解决方案

Change the following RTL files:

• ddr2_idelay_ctrl.v
• ddr2_phy_dq_iob
• ddr2_phy_dqs_iob.v

Remove the following string from these files:

"(* IODELAY_GROUP = IODELAY_GRP *)"

UCF Changes

Add the following IODELAY_GROUP constraints to the UCF file:

INST "*/u_idelayctrl" IODELAY_GROUP=IODELAY_MIG;

INST "*/u_idelay_dqs" IODELAY_GROUP=IODELAY_MIG;

INST "*/u_iodelay_dq_ce" IODELAY_GROUP=IODELAY_MIG;

INST "*/u_idelay_dq" IODELAY_GROUP=IODELAY_MIG;

Virtex-5 DDR SDRAM Changes

Change the following RTL files:

• ddr_idelay_ctrl.v
• ddr_phy_dq_iob.
• ddr_phy_dqs_iob.v

Remove the following string from these files:

"(* IODELAY_GROUP = IODELAY_GRP *)"

UCF Changes

Add the following IODELAY_GROUP constraints to the UCF file:

INST "*/u_idelayctrl" IODELAY_GROUP=IODELAY_MIG;

INST "*/*.u_idelay_dqs" IODELAY_GROUP=IODELAY_MIG;

INST "*/*.u_idelay_gate" IODELAY_GROUP=IODELAY_MIG;

INST "*/u_idelay_dq" IODELAY_GROUP=IODELAY_MIG;

Virtex-5 QDRII SRAM Changes

Change the following RTL files:

• qdrii_idelay_ctrl.v
• qdrii_phy_cq_io.v
• qdrii_phy_v5_q_io.v

Remove the following string from these files:

"(* IODELAY_GROUP = IODELAY_GRP *)"

UCF Changes

Add the following IODELAY_GROUP constraints to the UCF file:

INST "*/U_IDELAYCTRL" IODELAY_GROUP=IODELAY_MIG;

INST "*/IODELAY_CQ" IODELAY_GROUP=IODELAY_MIG;

INST "*/IODELAY_Q" IODELAY_GROUP=IODELAY_MIG;

Virtex-5 DDRII SRAM Changes

Change the following RTL files:

• ddrii_idelay_ctrl.v
• ddrii_phy_cq_io.v
• qdrii_phy_dq_io.v

Remove the following string from these files:

"(* IODELAY_GROUP = IODELAY_GRP *)"

UCF Changes for X36 Parts (MEMORY_WIDTH parameter value of 36)

Add the following IODELAY_GROUP constraints to the UCF file:

INST "*/U_IDELAYCTRL" IODELAY_GROUP=IODELAY_MIG;

INST "*/genblk*.CQ_INST[*].Q_PER_CQ_INST[*].U_IODELAY_CQ" IODELAY_GROUP = IODELAY_MIG;

INST "*/genblk*.CQ_N_INST[*].Q_PER_CQ_N_INST[*].U_IODELAY_CQ_N" IODELAY_GROUP = IODELAY_MIG;

INST "*/genblk*.CQ_INST[*].U_IODELAY_CQ" IODELAY_GROUP = IODELAY_MIG;

INST "*/genblk*.CQ_N_INST[*].U_IODELAY_CQ_N" IODELAY_GROUP = IODELAY_MIG;

UCF File Changes for X18 Parts (MEMORY_WIDTH parameter value of 18)

Add the following IODELAY_GROUP constraints to the UCF file:

INST "*/U_IDELAYCTRL" IODELAY_GROUP=IODELAY_MIG;

INST "*/genblk*.CQ_INST[*].Q_PER_CQ_INST[*].U_IODELAY_CQ" IODELAY_GROUP = IODELAY_MIG;

INST "*/genblk*.CQ_INST[*].U_IODELAY_CQ" IODELAY_GROUP = IODELAY_MIG;

Virtex-5 Multiple Interface Designs Including Both DDR2 SDRAM and QDRII SRAM

Change the following RTL files:

• ddr2_idelay_ctrl.v
• ddr2_phy_dq_iob.v
• ddr2_phy_dqs_iob.v
• qdrii_idelay_ctrl.v
• qdrii_phy_cq_io.v
• qdrii_phy_v5_q_io.v

Remove the following string from these files:

"(* IODELAY_GROUP = IODELAY_GRP *)"

UCF Changes

Add the following IODELAY_GROUP constraints to the UCF file:

INST "*/u_idelayctrl" IODELAY_GROUP=IODELAY_MIG;

INST "*/u_idelay_dqs" IODELAY_GROUP=IODELAY_MIG;

INST "*/u_iodelay_dq_ce" IODELAY_GROUP=IODELAY_MIG;

INST "*/u_idelay_dq" IODELAY_GROUP=IODELAY_MIG;

INST "*/IODELAY_CQ" IODELAY_GROUP=IODELAY_MIG;

INST "*/IODELAY_Q" IODELAY_GROUP=IODELAY_MIG;

NOTE: Any hierarchy path changes to the MIG generated designs should be considered by the users.