I have a design where I declared a component in a package the same name as one of my instances. I get the following error with Virtex-6/Spartan-6, but do not have any issues with any of the older devices:
"ERROR:HDLCompiler:40 - "<file>.vhd" Line xx: <name> is not a component"
The following example results in an error, notice the name of the component and instance are both my_name:
library ieee;
use ieee.std_logic_1164.all;
package my_pack_0003 is
component my_name is
port(in_port : in std_logic;
out_port: out std_logic);
end component;
end package;
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.my_pack_0003.all;
entity ex_0003 is
port(in_port : in std_logic;
out_port: out std_logic);
end ex_0003;
architecture beh of ex_0003 is
begin
my_name : my_name port map(in_port =>in_port, -- Note: Error points here
out_port=>out_port);
end;
In 11.2 XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, please refer to (Xilinx Answer 32927)
The above code is not VHDL LRM compliant. To solve this, simply change the name of either the instance or the component.
For example, in the above code you can edit the source to:
library ieee;
use ieee.std_logic_1164.all;
package my_pack_0003 is
component my_name is
port(in_port : in std_logic;
out_port: out std_logic);
end component;
end package;
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.my_pack_0003.all;
entity ex_0003 is
port(in_port : in std_logic;
out_port: out std_logic);
end ex_0003;
architecture beh of ex_0003 is
begin
my_inst : my_name port map(in_port =>in_port, -- Note: Error points here
out_port=>out_port);
end;
| AR# 32997 | |
|---|---|
| 日期 | 12/15/2012 |
| 状态 | Active |
| Type | 综合文章 |