AR# 33607


MIG Virtex-6 DDR3/DDR2 - Guidelines on swapping data byte placement (rtl and UCF requirements)


MIG allows users to select banks for placement of Data, Address/Control, System Control, and System Clock. Based on these bank selections, MIG generates a design with an ideal pin-out and design placement.
The Virtex-6 FPGA Memory Solutions User Guide (UG406) states the following allowed changes for moving pins in the design generated by MIG:
  • The address and control pin assignments can be swapped with each other as needed.
  • DQ and DM pin assignments within the same byte can be swapped with each other.

In addition to these pin changes, it is also possible to swap data bytes (DQS groups) in the MIG output. This involves more extensive modifications. The required changes are detailed in this Answer Record. The steps assume that the same I/O columns (e.g., center left and center right) and pins are still being used. This means that all of the same pins are used, DQS groups are simply swapped.

NOTE: Starting with ISE 12.1, MIG includes the Verify UCF and Update Design and UCF feature. This tool enables users to modify the MIG generated UCF to match the layout on their board and run through the tool to produce an updated MIG design. With this flow, all rtl parameters and UCF settings in the generated design will properly reflect the board pin-out.It is possible to perform a "logical" swapping where, for example, byte[0] in the MIG design is routed to byte[3] on a DIMM. This type of swapping eases PCB routing does not require the changes noted in this Answer Record.

NOTE: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Step 1 - Modify Pins LOCs

Swap the pin LOCs for the DQS groups appropriately in the MIG provided UCF.

Step 2 - Modify Capture Logic Constraints

In the MIG provided UCF under the comment header "Place CPT OSERDES and IODELAY", are pairs of LOC constraints (each pair consisting of an OLOGIC and an IODELAY LOC). Each of these pairs corresponds to a DQS group. An example of these constraints for two bytes is shown below:
##Site: AJ10 -- Bank 33
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt"
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt"
##Site: AD12 -- Bank 33
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt"
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt"
The indices referred to in the constraints (e.g., "cpt[0]" and "cpt[1]" in the example above), should be swapped according to how the DQS groups have been swapped.

Step 3 - Modify HDL Parameters

Overview: There are up to eight pin-out specific top-level parameters in the MIG design, these are the parameters nDQS_COLx and DQS_LOC_COLx. Where x = 0, 1, 2, 3, corresponds to one of the up to four I/O columns in a device (Inner-Left, Inner-Right, Outer-Left, Outer-Right). The only required correlation between x and the I/O column is that [0, 1] correspond to the two inner columns (index [0] can correspond to either the inner left or inner right column). These parameters specify the grouping of the DQS groups so that a common BUFR will drive the IOB logic for the correct DQS groups (one BUFR is used for all the DQs within the same I/O column, regardless of the number of DQS groups on that I/O column).
Required changes: These parameters only need to be modified if the DQS group swaps are within 2 inter-columns (e.g., swapping two bytes, one of which is located on the inner left, and one on the inner right column). If there are no inter-column swaps, these parameters do not need to be changed. In the case of inter-column swaps, these parameter values will need to be changed based on the new pin-out (see below). In a two-column design, only nDQS_COL0, DQS_LOC_COL0, nDQS_COL1, and DQS_LOC_COL1 will be used. The other 4 parameters will be set to 0 by MIG.
Description of parameters:
Description of Parameters
Description of Parameters

Example #1:
Single column, 9-bytes, as shown below (banks shown by DDR3 interface shaded):
Single Column Example
Single Column Example

The resultant parameters must be set to:
- nDQS_COL0 = 9
- DQS_LOC_COL0 = 72h080706050403020100
- nDQS_COL1 = nDQS_COL2 = nDQS_COL3 = 0
Example #2:
Two column, 9-bytes design as shown below (banks shown by DDR3 interface shaded. Bytes [8] [6] [4] [2] [1] [0] are on inner right column. Bytes [7] [5] [3] are on inner left column.
Two Column Example
Two Column Example

The resultant parameters must be set to:
- nDQS_COL0 = 6
- nDQS_COL1 = 3
- DQS_LOC_COL0 = 48h080604020100
- DQS_LOC_COL1 = 24h070503
- nDQS_COL2 = nDQS_COL3 = 0



Answer Number 问答标题 问题版本 已解决问题的版本
34308 MIG Virtex-6 DDR3/DDR2 - Verify pin-out/banking requirements are met N/A N/A
34265 MIG Solution Center - MIG Virtex-6 and Spartan-6 Top Issues N/A N/A
AR# 33607
日期 12/15/2012
状态 Active
Type 综合文章
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