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AR# 33774

Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - 250 MHz Is Not a Valid Reference Clock Option

描述

Known Issue: v1.2, v1.1

The v1.2 Spartan-6 FPGA Integrated Block Wrapper Customization GUI allows the user to select a 250 MHz reference clock. This is not a valid option for Spartan-6 FPGAs. According to the Spartan-6 data sheet, the maximum allowed frequency for the GTP reference clock is 160 MHz.

解决方案

Do not select the 250 MHz reference clock option. The Spartan-6 FPGA supports either a 100 MHz or a 125 MHz reference clock for PCI Express applications. Refer to (Xilinx Answer 18329) for more information regarding clocking and Spartan-6 and PCI Express and see (Xilinx Answer 33761) for more information on enabling 100 MHz.

Note that if a board has already been laid out using 250 MHz reference clock from the IDT PLL as described in (Xilinx Answer 18329), this PLL is programmable and users should select the 125 MHz output instead of the 250 MHz output.

Revision History
07/05/2011 - Updated title
11/09/2009 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
33776 Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express Master Answer Record N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
33776 Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express Master Answer Record N/A N/A
AR# 33774
日期 05/22/2012
状态 Active
Type 设计咨询
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
的页面