AR# 34267


MIG v3.2-3.4 Virtex-6 DDR3 - Can banks be shared between multiple memory controllers?


Starting with the MIG v3.2 release, DDR3 multi-controller support is available.

The Bank Selection page of the GUI only allows placement of data bytes belonging to the same controller within an FPGA bank.

Is it possible to place data bytes from different DDR3 controllers in the same bank?


MIG v3.2-3.4 do not support sharing banks between any two controllers.

Address/Control banks use too many pins to share with a separate controller.

Data banks between controllers had specific architectural reasons pre MIG-3.4 which prohibited any data bank sharing across controllers.

This dealt with the design usage of performance path clock outputs from the 2 MMCMs (system and read).
Starting in MIG 3.4, the design only uses 1 MMCM per controller.

As a result it is possible to share data banks from two controllers in a single FPGA bank.

Sharing data banks between controllers is now supported starting in MIG v3.5. 



Answer Number 问答标题 问题版本 已解决问题的版本
34329 MIG Virtex-6 DDR2 - Multi-Controller Support N/A N/A
34327 MIG Virtex-6 DDR2/DDR3/QDRII+ - Multi-Controllers N/A N/A
34266 Xilinx Virtex-6 MIG Solution Center - Design Assistant N/A N/A
AR# 34267
日期 10/15/2014
状态 Active
Type 综合文章
器件 More Less
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