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AR# 34318

MIG 7 Series and Virtex-6 DDR2/DDR3 - Description of Output Directory/Files

描述

This section of the MIG Design Assistant focuses on the output directory structure and generated files for 7 Series and Virtex-6 FPGA DDR3/DDR2 designs. Below you will find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

For a description of output directory/files for 7 Series and Virtex-6 DDR3/DDR2 designs, please refer to the "DDR2 and DDR3 SDRAM Memory Interface Solution > Getting Started with the CORE Generator tool > Directory Structure and File Descriptions" section of the Virtex-6 Memory Interface Solutions User Guide and in the 7 Series FPGAs Memory Interface Solutions User Guide.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34323 MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Output N/A N/A
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A

相关答复记录

AR# 34318
日期 10/04/2012
状态 Active
Type 解决方案中心
器件 More Less
IP
的页面