AR# 34320

MIG 7 Series and Virtex-6 DDR2/DDR3 - Usage of User Design

描述

This section of the MIG Design Assistant focuses on the usage of the User Design for 7 Series and Virtex-6 DDR3/DDR2 designs. Below, you will find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

The MIG generated User Design does not include a synthesizable testbench (provided with the Example Design) to generate various traffic data patterns to the memory controller. The User Design is meant to interface to your user logic using the User Interface.

For information on driving the User Interface, please see (Xilinx Answer 33698)

For a complete description on usage of the user design for 7 Series and Virtex-6 DDR3/DDR2 designs, please refer to the DDR2 and DDR3 SDRAM Memory Interface Solution > Core Architecture section in the Virtex-6 Memory Interface Solutions User Guide and in the 7 Series FPGAs Memory Interface Solutions User Guide.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34323 MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Output N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
33698 MIG 7 系列和 Virtex-6 FPGA DDR2/DDR3 - 如何驱动用户接口? N/A N/A

相关答复记录

AR# 34320
日期 10/04/2012
状态 Active
Type 解决方案中心
器件 More Less
IP