AR# 34327

MIG Virtex-6 DDR2/DDR3/QDRII+ - Multi-Controllers

描述

This section of the MIG Design Assistant focuses on using multi-controller implementations with Virtex-6 DDR3/DDR2/QDRII+ FPGA designs. Below you will find information related to your specific question.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

(Xilinx Answer 34329) - DDR2 Multi-Controller
(Xilinx Answer 33268) - Sharing MMCMs
(Xilinx Answer 34267) - Sharing Banks across multiple controllers

MIG supports DDR3 and QDRII+ multi-controllers through the MIG tool. Up to 8 controllers of either DDR3, QDRII+, or a combination of both can be designed within the tool. During bank selection, the tool recognizes if the number of controllers specified cannot fit in the selected FPGA device. The DDR3 and DDR2 Memory Interface Solution > Getting Started section of The Virtex-6 Memory Interface User Guide discusses generation of multi-controllers.

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AR# 34327
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
IP