UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34405

ML605 Hardware User Guide (UG534) - GTXE1 Package placement is incorrectly shown on page 33

描述

Table 1-8: "PCIe Edge Connector Connections" on page 33 ofthe ML605 Hardware User Guide v1.2.1, January 21, 2010 (UG534) shows the following GTXE placement for ML605:

GTXE1_X0Y15
GTXE1_X0Y14
GTXE1_X0Y13
GTXE1_X0Y11
GTXE1_X0Y10
GTXE1_X0Y9
GTXE1_X0Y8
GTXE1_X0Y7

However, the correct placement locations are as follows:

GTXE1_X0Y15
GTXE1_X0Y14
GTXE1_X0Y13
GTXE1_X0Y12
GTXE1_X0Y11
GTXE1_X0Y10
GTXE1_X0Y9
GTXE1_X0Y8

解决方案

When generating the "Virtex-6 Integrated Block for PCI Express" from within CORE Generator and choosing the ML605 as the selected development board, the UCF that is created is correct and no modifications need to be made.

ML605 Hardware User Guide (UG534) v1.3 includes this fix.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34836 Virtex-6 FPGA ML605 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 34405
日期 12/15/2012
状态 Active
Type 综合文章
IP
Boards & Kits
的页面