AR# 34540


MIG Virtex-6 DDR2/DDR3 - Resynchronization (RSYNC) logic usage and placement


The MIG Virtex-6 DDR2/DDR3 design uses an internally generated clock to capture the data on DQ during reads. In previous MIG designs (ie - Virtex-5 DDR2), the DQS strobe was used to capture data. Capturing data with an internally generated clock is beneficial because it is a true free-running clock and has no pre-/post-amble glitches as DQS does. The MIG Vitrex-6 design uses two clocks in the data capture of a DQS byte:
  • Capture Clock
  • Resynchronization Clock.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


An MMCM uses the input system clock to generate the capture clock(s) and resynchronization clock(s) using the CLKPERF output. This CLKPERF output is a low jitter clock source that goes directly from the MMCM to the I/O without using a buffer. This MMCM is located in the infrastructure.v/.vhd module in the output 'rtl/ip_top' directory. The MMCM CLKPERF output is routed to OSERDES/IODELAY elements. These IODELAY elements drive BUFIO (capture logic) and BUFR (resynchronization logic) local clock buffers to create the CPT and RSYNC clocks. The IODELAYs allow each of these clocks to be adjusted individually to provide for reliable capture of the read data eye from the memory. The RSYNC clock is used for final stage data capture in the DQ ISERDES and to transfer read data into fabric.

For a view of this capture/rsync logic, see the PHY Clocking Architecture figure (Figure 1-47) in The Virtex-6 FPGA Memory Interface Solutions User Guide. For more information on this logic, see the DDR2 and DDR3 Memory Interface Solution > Core Architecture > PHY section in The Virtex-6 FPGA Memory Interface Solutions User Guide.


  • One resynchronization clock is used per interface per I/O column containing Data Groups. Meaning if an interface contains Data Group placement in 2 I/O columns, 2 RSYNC clocks are required.
  • Each RSYNC clock requires an OSERDES/IODELAY and BUFR.
  • In order to use these IODELAY and BUFR elements, a Clock Capable-P (P_SRCC or P_MRCC) site must be prohibited and logic within the prohibited site locked for capture logic usage


The MIG output locks the required number of CCIO pins and associated IODELAY and OSERDES sites for the interface generated. These LOCs are contained in the output User Constraints File (design.ucf). Here is an example rsync logic placement:

INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync"
LOC = "OLOGIC_X1Y143";
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync"
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync"
LOC = "BUFR_X1Y7";

By default, MIG uses Single Region Clock Capable I/O (P_SRCC) sites because all of the related logic data group logic exists within the same bank. Multi-Region P_CCIO sites may also be used. If it is desired to move the Capture Logic prohibits and site LOCs, users should modify the sites within the output UCF and run the updated UCF through the Verify UCF and Update UCF and Design tool. For more information, see (Xilinx Answer 34386) Information:
While the design does not capture data using DQS, it does monitor the phase of DQS during reads to account for any phase shift due to voltage/temperature changes. If the phase varies, the capture clock phase is adjusted using the MMCM Phase Shift.

Because DQS is not used to capture data, it only needs to be placed on ap/n I/O pair rather then a Clock Capable I/O (CCIO) pair.

For more information on the capture logic, please see:



AR# 34540
日期 03/06/2013
状态 Active
Type 综合文章
器件 More Less
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