2. 技术支持
  3. AR# 3526: MAP M1.4 - Application error on XC4000E design during the "Optimizing" phase.
  4. AR# 35260: MIG Virtex-6 DDR2/DDR3 - Clocking and Reset

AR# 35260

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MIG Virtex-6 DDR2/DDR3 - Clocking and Reset

描述

This section of the MIG Design Assistant will guide you to details on the clocking and reset for the Virtex-6 DDR3/DDR2 designs. Please select from the below options to find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

(Xilinx Answer 35242) - Clock Requirements

  • Includes information on the design's clocking scheme as well as changing the input clock frequency
(Xilinx Answer 33268) - Sharing MMCMs

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
33268 MIG Virtex-6 DDR2/DDR3 - Is it possible to combine MMCMs to save MMCM resources in multi-controller designs? N/A N/A
35242 MIG Virtex-6 DDR2/DDR3 - Clock Requirements and Modifying the Input Clock Frequency N/A N/A
AR# 35260
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
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