If edits are made to a lower level schematic but not the top level schematic, Project Navigator does not correctly update the project level HDL for the design.
To work around this issue, perform one of the following:
Either of these options forces the top level ".vf" (Verilog) or ".vhf" (VHDL) to be re-created.
This issue was resolved in ISE Design Suite 13.1 and re-introduced in ISE Design Suite 14.1 for VHDL target language projects.
The issue is resolved in ISE Design Suite 14.6.