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AR# 35496

14.5 Project Navigator - Changes on lower level schematics are not recognized


I make a change to a schematic file in a lower level (not the top) of the design hierarchy. After saving the schematic, the project processes correctly to go out-of-date and runs as expected. However, when looking at the design results, I see that my changes were not incorporated.


If edits are made to a lower level schematic but not the top level schematic, Project Navigator does not correctly update the project level HDL for the design.

To work around this issue, perform one of the following:

  • Touch the top level schematic in some way (e.g., move a net) and save before running project processes again.
  • Run Clean-up Project Files before running project processes again.

Either of these options forces the top level ".vf" (Verilog) or ".vhf" (VHDL) to be re-created.

This issue was resolved in ISE Design Suite 13.1 and re-introduced in ISE Design Suite 14.1 for VHDL target language projects.

The issue is resolved in ISE Design Suite 14.6.

AR# 35496
日期 06/18/2013
状态 Active
Type 已知问题
  • ISE Design Suite - 14.2
  • ISE Design Suite - 14.3
  • ISE Design Suite - 14.4
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 14.5
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