AR# 35594: 12.1 EDK - The Spartan-6 SP605 board contains an incorrect clock pin location for the PCIe core
AR# 35594
12.1 EDK - The Spartan-6 SP605 board contains an incorrect clock pin location for the PCIe core
描述
The Spartan-6 FPGA SP605 board contains an incorrect pin location for the PCIe core.
解决方案
Download and unzip the new SP605 fileXilinx_SP605_v2_2_0.zip, and replace the old onein the < XILINX_EDK >\board\Xilinx\boards\Xilinx_SP605\data directory. This issue is resolved in 12.2.