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AR# 35722

Design Assistant for PCI Express - How to add a PCI Express cores to Project Navigator?

描述

Can a core for PCI Express be implemented using Project Navigator?

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

解决方案

The cores can be implemented using ISE Project Navigator. It is not recommended to add the generated core's xco to an ISE project because it may cause an error similar to this:

ERROR:HDLCompiler:559 - "s6_pcie_v1_2.v" Line 421: Could not find module/primitive <pcie_bram_top_s6>.
Module s6_pcie_v1_2 remains a blackbox, due to errors in its contents
Instead, generate the core in CORE Generator tool and add all of the core's wrapper source code from source directory.

Revision History
08/13/2010 -Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

相关答复记录

AR# 35722
日期 12/15/2012
状态 Active
Type 综合文章
器件
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • More
  • Virtex-5 TXT
  • Virtex-6 SXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Spartan-6 LXT
  • Less
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Endpoint Block Plus Wrapper for PCI Express
的页面