AR# 35747


MIG Virtex-6 DDR2/DDR3 - Speeding Up Simulation


The MIG output provides a simulation testbench in the "example_design/sim" and "user_design/sim" directories. The testbench has specific parameters set to speed up the simulation time. These parameters are documented in theVirtex-6 FPGA Memory Interface Solutions User Guide(UG406), in the Getting Started with the CORE Generator Software section of the DDR2/DDR3 SDRAM Memory Interface Solution chapter:

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


MIG v3.6 and moving forward:
Starting in MIG v3.6, a new simulation parameter is added to speed up simulations.

// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Skip memory init &
// calibration sequence
// # = "FAST" - Skip memory init & use
// abbreviated calib sequence

Set this parameter to "SKIP" in the sim_tb_top.v/.vhd module to ensure the fastest simulation results.

NOTE: Ensure this parameter is set to OFF in the top-level rtl to ensure the initialization and calibration processes are not skipped in hardware.

Pre-MIG v3.6:
Parameters set by default in sim_tb_top.v/.vhd:

// # = "SKIP_PU_DLY" - Skip the memory initialization sequence,
// = "NONE" - Complete the memory initialization sequence.
parameter SIM_CAL_OPTION = "FAST_CAL";
// # = "FAST_CAL" - Skip the delay Calibration process,
// = "NONE" - Complete the delay Calibration process.

Additional parameters to speed up simulation:

NOTE: Only change these parameter settings if you do not need to simulate write leveling or phase detection.
To turn Write Leveling off, change the WRLVL parameter to OFF:
parameter WRLVL = "OFF";
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM

For more information on Write Leveling, see (Xilinx Answer 35094). To turn the Phase Detector circuit off, which disables the periodic reads required for the phase detector, change the PHASE_DETECT parameter to OFF:
parameter PHASE_DETECT = "OFF";

For more information on the phase detector circuit, see (Xilinx Answer 34480).
For ModelSim users, change following in the file:
  • Set ps as simulation resolution.Some designs set "-t fs" in vsim command line. Change it to "-t ps".
  • Remove "log -r /*" to turn off signal logging for all signals not in the wave window by default. This requires that you restart and re-run the simulation after adding any additional signals you want to see to the waveform.
If possible, use ModelSim SE instead of ModelSim PE.



Answer Number 问答标题 问题版本 已解决问题的版本
35094 MIG Virtex-6 and 7 Series DDR3 - Write Leveling N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
34480 MIG Virtex-6 DDR2/DDR3 - Phase Detection Circuit and Periodic Reads N/A N/A
34284 MIG Design Assistant - Virtex-6 DDR2/DDR3 Simulation N/A N/A
AR# 35747
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
People Also Viewed