描述

General Description:

How do I access an active Low GSR (global set/reset) for an XC4000E/X or a GR (global reset) for an XC5200 on the STARTUP block?

NOTE: For XC3000 devices, the global reset signal is a dedicated pin on the device. Also, all flip-flops and latches reset to 0 after configuration.

解决方案

By default, GSR/GR pin is active High. To change the polarity of these signals in your VHDL or Verilog code, instantiate or infer an inverter to the net that sources the GSR/GR pin of the STARTUP block.

The inversion will be absorbed inside the STARTUP block; a function generator will not be used to generate the inverter.

As the STARTUP block does not contain any outputs that are being used in this example, the "noprune" property is declared in library file to prevent the compiler from removing the STARTUP block.

Please see (Xilinx Answer 2370) for a reference to GTS in a Verilog design.

Please see (Xilinx Answer 1670) for reference to the outputs (DONEIN, Q1Q4, Q3, Q2) on the STARTUP block.

XC4000 -- Verilog code for active Low reset

This will work for XC5200, although the reset signal on the startup block is labeled "GR." Synplify will map the GSR signal name to GR in the netlist.

`include "/products/synplify.ver3_0/lib/xilinx/xc4000.v"

module use_active_low_gsr (reset);

input reset;

// the signal reset initializes all registers using the

// global STARTUP signal

STARTUP U1 (.GSR (!reset));

endmodule

XC4000 -- VHDL code for active Low reset

This will work for XC5200, although the reset signal on the startup block is labeled "GR." Synplify will map the GSR signal name to GR in the netlist.

library IEEE;

use IEEE.std_logic_1164.all;

library xc4000;

use xc4000.components.all;

entity use_active_low_gsr is

port (

reset : in STD_LOGIC

);

end use_active_low_gsr;

architecture xilinx of use_active_low_gsr is

begin

-- the signal reset initializes all registers using the

-- global STARTUP signal

U1 : STARTUP port map (GSR => not(reset));

end xilinx;