I generate a MIG controller through the CORE Generator software, then add the ".xco" to an ISE project and implement my design. MAP fails with some incompatible I/O standards type set because it does not pick up any constraints from the UCF associated for the XCO.
This also occurs when the MIG is generated from with Project Navigator using Project -> New Source.
To work around this issue, perform the following:
- Edit thethe UCF in the ./user_design folder, and add the top-level instance name to each path.
- Save the edited UCF to a new name.
- Add the new ucf file to the project directory.
NOTE: The UCF file needs a different name because the original is linked to the project through the MIG core's ".xco" file (even though it is not used). As an alternative flow, you could edit and save the UCF to the same name, remove the ".xco" file from the project, and add the Verilog/VHDL HDL wrapper for the core and the edited UCF file to the project.