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AR# 36573

MIG v3.5, Virtex-6 DDR3/QDRII+ - Cannot place System Clock in between DCI Cascade Master and Slave banks

描述

When a MIG design is generated with the System Clock group placed between Master and Slave DCI Cascade banks, PAR results in an error as follows:

ERROR:Place:1104 - The following banks: Bank 24, Bank 25 have been constrained to implement DCI Cascade, but the IOs locked to these banks with incompatible VCCO:

Bank 24: IO Standard 0: Name = HSTL_I_DCI, VREF = 0.75, VCCO = 1.50, TERM = SPLIT, DIR = INPUT, DRIVE_STR = NR
IO Standard 1: Name = HSTL_I_DCI, VREF = 0.75, VCCO = 1.50, TERM = SPLIT, DIR = INPUT, DRIVE_STR = NR
Bank 25: IO Standard 0: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
IO Standard 1: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = OUTPUT, DRIVE_STR = NR
IO Standard 2: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
IO Standard 3: Name = LVDS_25, VREF = NR, VCCO = NR, TERM = NONE, DIR = INPUT, DRIVE_STR = NR


All DCI_CASCADE slave banks must have VCCO settings that are compatible with the VCCO settings of the DCI_CASCADE master bank.

For more information on the DCI_CASCADE constraint, see the Constraint Guide.

For more information on VCCO compatibility rules, see the architecture user's guide.

An analysis can be done in PinAhead to evaluate which set of I/O's are locked to each of these I/O banks.

解决方案

This issue is fixed in the 12.3 MIG v3.6 software release.

In the meantime, re-generate the MIG controller with the System Clock group so that it is not in the middle of the Master and Slave DCI Cascade banks.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
36211 MIG v3.5 - Release Notes and Known Issues for ISE Design Suite 12.2 N/A N/A
AR# 36573
日期 08/20/2014
状态 Active
Type 综合文章
器件 More Less
IP
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