To resolve this issue, the refresh period must be reduced.
Step 1 - Subtract 25 from the Refresh Counter.
In testing, subtracting 25 from the period calculation has resulted in a true 7.8 microseconds refresh period.
To reduce the refresh period, modify the MEM_REFI_VAL calculation provided in the mcb_raw_wrapper.v/.vhd module.
The example below is for Verilog, but similar changes should be made for VHDL.
localparam MEM_REFI_VAL = ((C_MEM_TREFI + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
localparam MEM_REFI_VAL = ((((C_MEM_TREFI + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD)) 25);
Step 2 - Avoid a tRFC Violation.
Simply subtracting 25 from the refresh counter causes tRFC violations.
To avoid these violations, time needs to be added to the top-level parameter C_MEM_TZQINIT_MAXCNT.
This parameter is set in the memcx_wrapper.v/.vhd module.
The example below is for Verilog but similar changes should be made for VHDL.
localparam C_MEM_TZQINIT_MAXCNT = 10'd512;
localparam C_MEM_TZQINIT_MAXCNT = 10'd512 + 10'd16; // 16 clock cycles are added to avoid trfc violations
The above noted changes will be made in MIG 3.6 which will be released with ISE software 12.3.