AR# 36642


Virtex-6 System Monitor - Maximum DCLK frequency revised down to 80 MHz


The initial specification for the DCLK was 250 MHz. This has been revised down to 80 MHz.


The maximum conversion rate of the System Monitor is still 200 ksPs because the ADCCLK is still 5.2 MHz.

The ADCCLK = DCLK / DCLK Divisior (the DCLK divisor is set in the Config Reg #2).

The effect of violating the maximum DCLK of 80 MHz is that it can result in a race condition in the System Monitor logic which results in incorrect readings. The problem occurs at temperatures between 55 C and 80 C only.



Answer Number 问答标题 问题版本 已解决问题的版本
34565 有关 Virtex-6 FPGA 设计咨询的主要答复记录 N/A N/A
AR# 36642
日期 05/20/2012
状态 Active
Type 设计咨询
器件 More Less
People Also Viewed