Add the SIM_DEVICE attribute to the instantiation of the RAMB16BWER primitive in the pcie_bram_s6.v[hd] file.
This is found in the generated core's source directory.
Add the attribute and set it to "SPARTAN6".
Verilog
RAMB16BWER #(
.SIM_DEVICE ("SPARTAN6"),
etc....
ramb16 : RAMB16BWER
generic map (
SIM_DEVICE => "SPARTAN6",
etc...
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
37938 | Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues | N/A | N/A |
37939 | Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.1 | N/A | N/A |
AR# 37595 | |
---|---|
日期 | 09/22/2014 |
状态 | Active |
Type | 已知问题 |
IP |