AR# 37936


Virtex-6 FPGA Integrated Block Wrapper v1.6 for PCI Express - Release Notes and Known Issues


This Release Notes and Known Issues Answer Record is for the Virtex-6 FPGA Integrated Block Wrapper v1.6 for PCI Express first released in ISE Design Suite 12.3, and contains the following information:
  • General Information
  • New Features
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:


New Features
  • ISE 12.3 software support
  • QPro Virtex-6 Hi-Rel device support
  • Enabled ISE Simulator (ISIM) support
Resolved Issues

  • Synplify flow now supported for entire synthesis / implementation
    • CR 531976
    • A script is now provided to synthesize and implement the generated example design with Synplify. The script calls XST to Synthesize the wrapper source code. Synthesis for the wrapper source code is only supported by XST.
  • Added support for QPro Virtex-6 Hi-Rel devices
    • CR 551821
    • Support for all QPro Virtex-6 Hi-Rel devices has now been enabled.
  • Added support for ISE Simulator (ISIM)
    • CR 448851
    • Support has been enabled for ISE Simulator (ISIM).
  • 8-lane Gen2 product is now supported in the Virtex-6 HXT devices.
    • CR 531975
    • Support for 8-lane Gen2 product, in Virtex-6 HXT devices is now available.
  • GTX Production Settings Updated
    • CR 556498
    • GTX settings have been updated per Production GTX settings, based on PCI Express protocol characterization.
  • GUI support for 8-lane Gen2 configuration
    • CR 563396
    • Issue resolved where GUI did not allow generation of an 8-lane Gen2 design for an LX365T-3 device and allowed generation of an 8-lane Gen2 design for a LX550T-2 device, which is not supported.
  • GUI support for PCIe Block locations for SX315T-FF1156
    • CR 560140
    • Issue resolved where the GUI claimed 4 PCIe Block locations available on the SX315T-FF1156, whereas this device only has 2 available PCIe Blocks.
  • Use of corename "core" in VHDL design causing implementation failure
    • CR 538681, 569546
    • Issue resolved where use of corename "core" for a VHDL design caused implementation failures. The use of corename "core_i" is however disabled, as this is used as the instance name of the core in the VHDL design.
  • Updates to improve timing on Root Port configuration
    • CR 572179
    • Updates have been made implementation scripts and delivered UCFs to improve timing on the Root Port configuration design.
  • Default simulation test has been upgraded
    • CR 571632, 532234
    • Default simulation test has been upgraded to include memory and I/O reads and writes.
  • cfg_msg_* interface ports on Root Port Model now visible
    • CR 571176
    • cfg_msg_* ports are now visible at the top level of the Root Port Model delivered with Endpoint product.
  • cfg_wr_rw1c_as_rw_n port in Root Port product now connected tHard Block
    • CR 571018
    • cfg_wr_rw1c_as_rw_n port in the Root Port product is now connected to the port on the Integrated Block for PCI Express.
  • 128-bit wrapper back-pressure on User Interface when Block is full
    • CR 569361
    • Issue resolved where the 128-bit wrapper was not back pressuring the User Interface when the Transmit buffers were full, causing data loss.
  • User non-posted OK signal undriven in VHDL Root Port model
    • CR 568793
    • Issue resolved where the User non-posted OK signal was undriven in the VHDL Root Port model, preventing memory read transactions from passing to the User Interface.
  • Fixed missing default case statement in FSM in 128bit PIexample design
    • CR 567366
    • Issue resolved where the default case statement was missing in the FSM in the 128bit PIO example design.
  • Redeclaration of signals in VHDL instantiation template
    • CR 555620
    • Issue resolved where the signals were re-declared in the VHDL instantiation template, causing synthesis errors when used.

Known Issues
(Xilinx Answer 34009) - Virtex-6 FPGA ML605 Board - PCI Express Link Will Not Train; Implementations for PCI Express Must Use the v1.3 Integrated Block Wrapper for PCI Express
(Xilinx Answer 37784) - Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - x8 Gen 2 Timing Closure
(Xilinx Answer 38223) - Virtex-6 Integrated Block Wrapper v2.1 and v1.6 for PCI Express - Disabling Legacy Interrupts in the GUI does not change Interrupt Pin register
(Xilinx Answer 38847) - Virtex-6 Integrated Block Wrapper v1.6 for PCI Express - PIO_EP.vhd Does not Connect trn_trem_n to core
(Xilinx Answer 38848) - Virtex-6 Integrated Block Wrapper v1.6 for PCI Express - Corrections for UG517
(Xilinx Answer 39164) - Virtex-6 Integrated Block Wrapper v1.6 and v2.1 for PCI Express - Need to set BANDWIDTH attribute on MMCM to Low
(Xilinx Answer 39656) - Viretx-6 FPGA Integrated Block Wrapper for PCI Express - Clock net TxOutClk_bufg is not constrained
(Xilinx Answer 39456) - Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Delay Aligner Work-around
(Xilinx Answer 40637) - Virtex-6 FPGA Integrated Block Wrapper v2.2 and v1.6 for PCI Express - DRC Error During Simulation using Provided Root Port Model

Resolved Issues
02/14/2011 - Added 39456 and 40637.
02/10/2011 - Updated description of resolved issue CR 531976
12/17/2010 - Added 39656
11/17/2010 - Added 38223, 38847, 38848,39164
10/19/2010 - Fixed issue with unmatched "strong" tag causing entire AR to be in bold.
10/05/2010 - Initial Release




AR# 37936
日期 05/20/2012
状态 Active
Type 版本说明
器件 More Less
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