AR# 37968


MIG Virtex-6 DDR2/DDR3 - Additional Calibration Stage (CLKDIV Calibration Stage) Added To Calibrate the Timing of the BUFIO to BUFR Transfer


Starting with MIG 3.6 (available with ISE Design Suite 12.3), an additional calibration stage (CLKDIV Calibration Stage) is added to the calibration scheme performed upon reset.This new stage is in between stage 1 and stage 2 and is performed to calibrate the timing of the BUFIO to BUFR transfer.

Note: Xilinx recommends existing Virtex-6 DDR2/DDR3 designs upgrade to MIG 3.6 to have this calibration stage included.Details on this recommendation are noted below.

Note: This Answer Record is a part of the Xilinx MIG Solution Center(Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


  • A new calibration stage "CLKDIV" is performed between pre-existing stages 1 and 2 of calibration and is completed on a per-byte basis
  • For each byte, the BUFR clock phase is moved until the BUFIO to BUFR transfer within the ISERDES in that byte breaks
    • BUFIO to BUFR transfer occurs on the very last rank of flip-flops within the ISERDES
  • The process is then repeated with the DYNCLKDIVSEL input of that byte's ISERDES set to 1
    • This inverts the sense of BUFR within those ISERDES
  • Whichever value of DYNCLKDIVSEL yields the most margin determines the final setting of DYNCLKDIVSEL for that byte
  • The BUFR phase is reset to its original phase at the start of calibration
  • There are essentially three clock domain transfer points in the ISERDES as DQ data is captured and eventually appears at the Q outputs of the ISERDES.
    • Stage 1: Data captured using CPT clock (full-rate capture)
    • Stage 2: Data transferred to half rate CPT clock domain
      • This uses a divide-by-2 version of the CPT clock. Each ISERDES generates its own version of this half-rate clock
    • Stage 3: Data transferred from divide-by-2 CPT clock to CLKDIV
    For details on the PHY architecture, refer to the DDR2/DDR3 Memory Interface Solution > Core Architecture > PHY section of theVirtex-6 FPGA Memory Interface Solutions User Guide(UG406):

    Previous scheme
    • The phase of BUFR (via its IODELAY setting) was statically calculated based on the frequency of operation
      • One BUFR is responsible for synchronizing up to 9 different BUFIO (up to 3 clock regions)
      • The value of BUFR was meant to be able to handle all possible values that these BUFIO could have (each BUFIO could vary up to 0.5*tCK in order to center its capture clock in the middle of the data eye)

    Why did Xilinx make this change?

    Adding this calibration stage has proven during characterization to provide significantly more margin.

    How does adjusting the polarity of DYNCLKDIVSEL during the CLKDIV Calibration Stage increase timing margin?
    (Xilinx Answer 39022) MIG v3.6-v3.7 Virtex-6 DDR2/DDR3 - How does adjusting the polarity of DYNCLKDIVSEL during the CLKDIV Calibration Stage increase timing margin?

    Is this change recommended for existing Virtex-6 DDR2/DDR3 designs?

    Yes, upgrading to MIG v3.6, which includes this additional calibration stage is recommended. All characterization performed by Xilinx includes this additional calibration stage. As noted above, this stage adds significant margin to the data capture and needs to be included in production designs.



    Answer Number 问答标题 问题版本 已解决问题的版本
    37173 MIG v3.6 - Release Notes and Known Issues for ISE Design Suite 12.3 N/A N/A


    AR# 37968
    日期 12/15/2012
    状态 Active
    Type 综合文章
    器件 More Less
    People Also Viewed