UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 38134

Design Advisory for Virtex-6 Configuration - PROGRAM_B pin held Low prior to power up does not delay configuration

Description

How can configuration be delayed at power up on a Virtex-6 device, and how is this different from prior families?

解决方案

On prior families the PROG or the INIT pins can be held low at power-up to delay configuration. With the Virtex-6 devices the PROG pin is edge sensitive as opposed to level sensitive. So, holding this pin low at power up will not continue to delay configuration.

The way to delay configuration is to hold the INIT pin low. INIT is an open drain driver and requires a pullup on the pin to pull the pin high once it is released by the device. The device will only drive the pin low, and will then release the pin when the device is ready to start configuration. The INIT pin must then go high for the mode pins to be sampled and the configuration process to begin.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34565 有关 Virtex-6 FPGA 设计咨询的主要答复记录 N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
38016 Virtex-6 程序引脚 (PROG_B) 在上电时如果被置低就不会延迟配置。 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
43174 7 series - PROGRAM_B pin held Low prior to power-up does not delay configuration N/A N/A
34565 有关 Virtex-6 FPGA 设计咨询的主要答复记录 N/A N/A
AR# 38134
创建日期 09/27/2010
Last Updated 10/15/2012
状态 Active
Type 设计咨询
器件
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less