AR# 38215: Design Assistant for XST Help resolving "HDLCompiler:91:Signal missing in the sensitivity list is added for synthesis purposes." warnings
AR# 38215
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Design Assistant for XST Help resolving "HDLCompiler:91:Signal missing in the sensitivity list is added for synthesis purposes." warnings
描述
Refer to this Answer Record for help resolving a "HDLCompiler:91:Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result." warning.
Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.
解决方案
This message appears when the signal is missing in the sensitivity list and where as it is added to the sensitive list for synthesis purpose. Hence, the HDL and the post simulations might differ.
WHAT NEXT:
Add the corresponding signal to the sensitivity list, and re-run XST.
always @(posedge clk, posedge rst) begin if(rst) OutData <= temp_reg; else OutData <= din; end
assign out = OutData; endmodule
'temp_reg' is not present in the sensitivity list and its value is being read in the always block, thismight result inincorrect logic creation andincorrect simulations of HDL. Adding temp_reg resolves this issue.