2. 技术支持
  3. AR# 3821: Foundation, MAP: Excessive logic removed (trimmed) from a design captured in Foundation schematic.
  4. AR# 38215: Design Assistant for XST Help resolving "HDLCompiler:91:Signal missing in the sensitivity list is added for synthesis purposes." warnings

AR# 38215

Design Assistant for XST Help resolving "HDLCompiler:91:Signal missing in the sensitivity list is added for synthesis purposes." warnings

描述

Refer to this Answer Record for help resolving a "HDLCompiler:91:Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result." warning.

Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.

解决方案

This message appears when the signal is missing in the sensitivity list and where as it is added to the sensitive list for synthesis purpose. Hence, the HDL and the post simulations might differ.

WHAT NEXT:

Add the corresponding signal to the sensitivity list, and re-run XST.

EXAMPLE:

Consider the following RTL:

module top (din, clk, rst, out);
input din;
input clk;
input rst;
output out;

reg temp_reg;
reg OutData;

always @(posedge clk, posedge rst) begin
if(rst)
OutData <= temp_reg;
else
OutData <= din;
end

assign out = OutData;
endmodule



'temp_reg' is not present in the sensitivity list and its value is being read in the always block, thismight result inincorrect logic creation andincorrect simulations of HDL. Adding temp_reg resolves this issue.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
38927 面向 XST 的 Xilinx 解决方案中心 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
40379 Design Assistant for XST Help understanding the XST report to resolve errors\warnings N/A N/A
AR# 38215
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
Tools More Less