2. 技术支持
  3. AR# 3873: 2.1i COREGEN, WORDPAD: "The document xxxx is in use by another application and cannot be accessed." / The CORE Generator does not release its "lock" on an XCO file
  4. AR# 38733: Design Advisory for Spartan-6 - LX100/LX100T SMAP x16 max CCLK frequency reduction

AR# 38733

Design Advisory for Spartan-6 - LX100/LX100T SMAP x16 max CCLK frequency reduction

描述

There has been a reduction of the max CCLK frequency for the following devices and configuration interface:

Spartan-6 LX100/LX100T SelectMAP x16-only -4/-3/-2

The maximum frequency has been reduced from 40 MHz to 35 MHz.

解决方案

The data sheet update can be seen in DS162, version 1.10, November 4, 2010 (http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf).

There are no PROMs or flash devices supported by the Spartan-6 FPGA in a x16 mode. However, the following could be affected:
- Custom system-level configuration solutions that drive the SelectMAP x16 bus at > 35 MHz.
- Processors that drive the SelectMAP x16 bus at >35 MHz
- ICAP designs that drive the SelectMAP x16 bus at > 35 MHz (This will be flagged in a DRC warning that indicates an ICAP timing violation at > 20 MHz. The ICAP DRC is set to the max Readback CCLK frequency).

No impact for these applications:
- No impact for BPI flash running in x16 wide because the system-level timing results in maximum operation of CCLK at ~6 MHz.
- No impact for < 16-bit wide configuration interfaces because internal configuration bus is multiple times slower
- No impact for any Xilinx PROMs in x1 or x8 mode.
- No impact for serial, SPI x1/x2/x4, JTAG modes.
- No impact for encrypted bitstreams because they are only supported via a serial or x8 interface.
- No impact for internal Readback CRC because maximum readback specification is 12 MHz.
- No impact for SW DRCs on ICAP config CLK. DRC warning already given when CLK > 12 MHz (max Readback frequency).

Some additional information on the priority of some specifications where the master CCLK max frequency was being overridden by interface-specific specifications. For example, the maximum frequency for the master CCLK in isolation might be 40 MHz, but when used with a parallel mode, the system-level limitations might impose a lower viable frequency maximum. The explanation of the priorities is described in DS162 via the following breakout of the Master CCLK maximum frequency specification. Previously, there was just one FMCCK row. It is now broken into specifications by interface type to explicitly indicate the overriding limitation.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A
AR# 38733
日期 05/20/2012
状态 Active
Type 设计咨询
器件