AR# 38861


Spartan-6 - IBERT - Coregen PAR Error: Timing not met


12.x IBERT for Spartan-6 FPGA may generate the following error, under several different conditions:

ERROR:sim - runPar : IBERT:par: Timing for this design was not met. Reduce the
number of GTs enabled, reduce your line rate, and/or choose a faster device.


This error can be safely ignored in most circumstances. This is a bug in IBERT only reports the error but continues to generate the bit file which will work correctly.
AR# 38861
日期 01/02/2013
状态 Active
Type 已知问题
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