AR# 39071: 12.3 EDK - How do I close timing on EDK AXI designs?
12.3 EDK - How do I close timing on EDK AXI designs?
I am failing timing on an EDK AXI design, how do I close timing?
-For AXI designs, it is critical to enable register slices between AXI masters and AXI slaves if timing is not being met between these interfaces. These are optional pipeline registers which help to isolate masters from the AXI Interconnect from a timing perspective. To enable register slices, open the configuration GUI of each AXI Interconnect, and choose the Master/Slave Specific Settings->Register Slices tab, see below. Then for each AXI channel (Write Address, Read Address, Read Data, Write Data, Write Response), start by choosing FULLY_REGISTERED for all masters and slaves of all channels to determine if timing can be met with Register Slices alone.
Note that Register Slices will increase latency, and so it may be worthwhile after timing is met to determine which settings are actually required to meet timing. This is typically accomplished through a trial and error method of enabling/disabling individual register slices. -Be sure to upgrade software tools and IP. There are multiple timing and device utilization improvements planned for EDK 12.4 and 13.1. -Optimize AXI Interconnect clocking. The AXI Interconnect allows clock domain crossing. Consider running a slower speed interconnect and low-performance peripheral clock connected to the MicroBlaze data peripheral (DP) AXI port. -When available, use AXI4-Lite on IP cores that the system can tolerate lower-throughput on.