STEP 1
In RXAUI v1.2 and earlier, the GTX attributes need to be modified to disable the delay aligner. To fix this problem, edit the <rxaui_core_name>/example_design/gtx_wrapper.v[hd]. The POWER_SAVE[5:4] needs to be modified and all other bits should be left as is.
For Verilog change:
.POWER_SAVE(10'bxxxx10xxxx),
To
.POWER_SAVE(10'bxxxx11xxxx),
For VHDL change:
POWER_SAVE => "xxxx10xxxx",
To:
POWER_SAVE => "xxxx11xxxx",
STEP 2
Modifying the POWER_SAVE attribute results in software errors in ISE software 12.4, 12.3 and 12.2. (Xilinx Answer 39434) provides a method for working around these errors.
STEP 3
In RXAUI v1.2 and earlier, the MMCM is using the internal feedback loop. A BUFG needs to be added to the MMCM feedback path.
For Verilog in <core_name>_example_design.v:
a) Add a wire for the output of the BUFG:
wire clkfb_bufgout;
b) Add a bufg instantiation for the feedback clock:
BUFG clkfb_bufg_i (
.I(clkfb),
.O(clkfb_bufgout));
c) Change the MMCM instantiation to drive the CLKFBIN with the output from the BUFG:
.CLKFBIN(clkfb_bufgout),
For VHDL in <core_name>_example_design.vhd: a)Add a new signal name declaration for the output of the BUFG:
signal clkfb_bufgout : std_logic;
b) Add a bufg for the feedback clock:
clkfb_bufg_i : BUFG
port map (
I => clkfb,
O => clkfb_bufgout);
c) Change the MMCM instantiation to drive the CLKFBIN with the output from the BUFG
CLKFBIN => clkfb_bufgout,
STEP 4
Part of the requirement to fix the Delay Aligner issue is that the GTX TXOUTCLK must drive the MMCM directly with no BUFG in the path. By default, in the wrapper, TXOUTCLK already drives the MMCM directly with no BUFG in the path. The only change needed is to modify the POWER_SAVE attribute. However, this means the MMCM is restricted to the same region as the MGTs and users must not add a BUFG to move the MMCM out of the region. Each GTX Quad spans an entire clocking region and there are two available MMCMs per clocking region, the MMCM used must be constrained to the same clock region otherwise a BUFG will automatically be inserted. These locations can be determined using the Virtex-6 Package and Pinout Guide (UG365): http://www.xilinx.com/support/documentation/user_guides/ug365.pdf
If users have modified the wrapper to add a BUFG to this path in order to move the MMCM out of the region with the MGTs, it must be removed and the MMCM should be located in the region with the MGT providing TXOUTCLK.
Revision History:
1/24/2011 - Added Step 3 - need to insert BUFG in MMCM feedback clock path