AR# 40445: Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.3
Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.3
This article contains issues resolved in the Virtex-6 FPGA Integrated Block v2.3 Wrapper for PCI Express that are also listed in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.
GTX transceiver settings have been updated to work around the Virtex-6 GTX Transceiver Delay Aligner Errata.
GTX Wrapper updated
The GTX Wrapper updated per latest recommendations for GTX Transceiver for PCI Express.
Default Reference Clock Frequency updated
The default reference clock frequency for Designs with Link Speed 5.0 Gb/s been changed from 250 MHz to 100 MHz.
PMA_RX_CFG attribute in GTX wrapper updated
The PMA_RX_CFG attribute in the GTX wrapper has been updated to be set based on Synchronous or Asynchronous clocking selected (Slot Clock selection).
Transaction Buffer Pipeline default setting for 8-lane Gen2 configuration
The default setting for Transaction Buffer Pipeline for 8-lane Gen2 configurations has been updated to "Buffer Write and Read"
INTERRUPT_PIN attribute update based on Legacy Interrupt option in GUI
Issue resolved where un-checking the Legacy Interrupt option was not updating the INTERRUPT_PIN attribute.
Revision History 01/18/2012 - Modified format to use a single AR for all known issues and referenced 45723 for all known issues. Any issue that was listed here is now in AR 45723. 12/02/2011 - Minor update to fix format for Documentation Center viewing. 06/21/2011 - Fixed known issue bullet formatting. Removed issue related to x1G2 VHDL linking up. This configuration works fine and there are no issues. 03/29/2011 - Added Answer Record 41509 03/04/2011 - Added Answer Records 41051 and 41052 03/01/2011 - Initial Release