This article contains issues resolved in the Virtex-6 FPGA Integrated Block v2.3 Wrapper for PCI Express that are also listed in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.
For other known and resolved issues that may not be in this list see (Xilinx Answer 45723)
01/18/2012 - Modified format to use a single AR for all known issues and referenced 45723 for all known issues. Any issue that was listed here is now in AR 45723.
12/02/2011 - Minor update to fix format for Documentation Center viewing.
06/21/2011 - Fixed known issue bullet formatting. Removed issue related to x1G2 VHDL linking up. This configuration works fine and there are no issues.
03/29/2011 - Added Answer Record 41509
03/04/2011 - Added Answer Records 41051 and 41052
03/01/2011 - Initial Release